There has been explosive growth in Internet traffic due to the increased number of Internet users, various service demands from those users, the implementation of new services, such as voice-over-IP (VoIP) or streaming applications, and the development of mobile Internet. Conventional routers, which act as relaying nodes connected to sub-networks or other routers, have accomplished their roles well, in situations in which the time required to process packets, determine their destinations, and forward the packets to the destinations is usually smaller than the transmission time on network paths. More recently, however, the packet transmission capabilities of high-bandwidth network paths and the increases in Internet traffic have combined to outpace the processing capacities of conventional routers.
This has led to the development of a new generation of massively parallel, distributed architecture routers. A distributed architecture router typically comprises a large number of routing nodes that are coupled to a high-bandwidth crossbar switch via a plurality of switch fabric modules. Each routing node has its own routing (or forwarding) table for forwarding data packets via other routing nodes to a destination address.
In a conventional 1 Gigabit Ethernet (GbE) router, each routing node uses a network processor (NP) that performs routing functions for both incoming (ingress) and outgoing (egress) data packets. A 1 GbE network processor typically uses micro-engines that forward data packets, both within the same routing node as well as to other routing nodes via the switch fabrics.
The single network processor arrangement is particularly advantageous for “hairpinning” a received data packet. If a routing node receives a data packet from an external source device, and both the source device and the destination device are coupled to the routing node via the physical media device (PMD) modules of the routing node, there is no need to transfer the data packet through the switch fabrics and/or cross-bar switch associated with the routing node. Instead, the micro-engines of the network processor simply transmit the received data packet back out through the PMD modules (i.e., like a “hairpin” turn) without using the switch fabrics.
However, the single network processor approach cannot keep up with the 10 Gbps data rate of newer 10 Gigabit Ethernet (GbE) routers. As a result, 10 GbE routers use two network processors, an ingress processor for routing incoming data packets received from a PMD module and an egress processor for routing outgoing data packets received from the switch fabric and/or cross-bar switch. Use of two network processors allows higher data rates, but also requires a different approach to hair-pinning data packets, since the micro-engines in the two processors are not handling both the incoming and the outgoing data packets.
An alternative way to hairpin data packets is to let the control plane processors forward the data packets between the network processors within the routing node. However, using a single processor to handle data packets and to perform control plane functions can only be used with very low speed routers. In fact, using a central processor for data plane and control plane functionality is even worse in terms of the data rates supported than a single network processor in a 1 GbE router configuration.
A new data plane interface could be added between the micro-engines in the egress and ingress network processors to allow the micro-engines of the two network processors to forward packets directly to the other network processor. However, using a new high-speed data interface between the micro-engines of the two network processors is impractical, as there is no convenient place to connect the new interface to the micro-engines. In essence, this approach requires added hardware and complexity, which leads to circuit board problems associated with higher speed interfaces.
Finally, the switch fabric modules could be used to allow loop-backs of data packets during normal operations. However, conventional switch fabrics do not provide this feature. Modification of the switch fabric is possible, but has the disadvantage of requiring a switch module even with a single routing node system. In addition, it has the disadvantage of shipping all of the data back and forth over the optical links, adding to the delays and optical traffic.
Therefore, there is a need in the art for an improved high-speed router. In particular, there is a need for a high bandwidth mechanism for routing (or hairpinning) data packets between the ingress and egress network processors within the same routing node.